A conventional, single input CMOS logic gate circuit for processing an input signal typically employs a P-channel field effect transistor (PFET) connected between a power supply source (V.sub.DD) and an output node. The PFET is operative to "pull-up" the voltage of the output node essentially to V.sub.DD in response to the input signal when applied to the input terminal (gate electrode) of the PFET as is well known. The circuit also includes an N-channel transistor (NFET), connected between the output node and ground. The NFET is operative to "pull-down" the voltage of the output node to a "low" level appropriately, typically ground, in response to the input signal when applied to the input terminal of the NFET as is also well known.
For multiple input NOR gates, the pull-up of the output node requires a multiplicity of PFETs, connected electrically in series drain to source, between the voltage supply V.sub.DD and the output node. The number of these PFETs is equal to the number of input signals to which the NOR gate is designed to respond, a separate input for each input signal. Also, a like plurality of N-channel transistors is connected electrically in parallel between the output node and ground.
Similarly, other multiple input CMOS logic gates require a multiplicity of P-channel and N-channel transistors. For such multiple input gates it is difficult to achieve high speed pull-up operation. The reason for this is that for high speed operation the RC delays characteristic of the PFET and NFET segments of the circuit have to be set about equal to each other. Since the resistances of the PFETs are in series, reduction in the total resistance of the PFET segment would require much larger PFET elements than NFET elements as is well understood. In turn, the total parasitic capacitance inherent in a chain of relatively large capacitance PFET's would undesirably increase and thereby dictate relatively slow operation. Consequently, there is a practical limit to operating speeds of multi-input CMOS logic gates, such as NOR gates.